Computer Architecture Intro 2C1C5F

**Welcome and Course Introduction** 1. **Introduction to the Semester and Instructor** - The instructor, Amira Shuri, is a postdoc researcher at the University of Toronto and will be a sessional lecturer at York University this semester. - Course website and Moodle setup are pending; updates will be communicated via email. - Teaching Assistants (TAs) will be announced next week to manage the workload for over 100 students. 2. **Lab Structure and Schedule** - Labs start in two weeks with eight total sessions: four before midterm and four after. - Each group has assigned lab sessions; attending your assigned lab is important to avoid grading issues. - Each lab includes a pre-lab (using RISC-V simulator), a lab test mode, and submission of assignments. - Makeup labs are available for emergencies, one before and one after midterm. 3. **Course Textbook and Schedule** - Textbook: "Computer Organization and Design" updated to RISC-V architecture by authors from Berkeley. - Tentative schedule includes chapters 2 and 3 initially, aligned with lab activities. 4. **Prerequisites and Simulator** - Basic programming knowledge required. - Use of RISC-V simulator for assembly language programming and lab exercises. 5. **Grading Breakdown** - Labs constitute roughly 30% of the grade (approx. 4-5% each). - Remaining grades come from midterm and final exams. - No quizzes planned yet. **Course Content Overview** 1. **RISC-V Architecture and Course Goals** - RISC-V is a modern, simplified open-source architecture replacing older mixed architectures. - Students will learn hardware-software interface, program translation from high-level to machine code, and hardware performance optimization. 2. **Computer History and Trends** - Evolution from early mainframes to personal and embedded computers. - Current trend: divergence into supercomputers (high cores, high performance) and embedded devices (smartphones, smartwatches). - Shift from local computing to cloud services. 3. **Performance Considerations** - Factors affecting performance include algorithms, programming languages, memory hierarchy, and I/O systems. - Understanding these components is key to evaluating program speed and efficiency. 4. **Important Concepts and Jargon** - Moore's Law: transistor count doubles approximately every 18 months, increasing performance until physical limits are reached. - Multicore processors and memory hierarchy (L1, L2, L3 caches) pose new challenges. 5. **Hardware-Software Interface** - Course explores layers from high-level languages (C, C++, Java) down to machine code. - Compilation and assembly translate human-readable code to binary instructions. - Historical note: early engineers wrote assembly manually; now compilers automate this. 6. **Computer Components and Data Flow** - Input/output devices, control unit (CPU), datapath, and memory (including cache) form the core architecture. - Memory hierarchy impacts program speed. 7. **Instruction Set Architecture (ISA)** - ISA provides an abstraction layer between hardware and software. - Different architectures (ARM, x86, RISC-V) have unique ISAs. - Using ISA allows software to be independent of underlying hardware changes. 8. **Semiconductor Manufacturing** - Silicon wafers are processed to create transistors acting as switches. - Manufacturing yield measures proportion of functional chips per wafer. - Technology has advanced to sub-10 nm scale in modern CPUs and mobile devices. **Summary** - The course provides a deep understanding of computer organization focusing on RISC-V architecture. - Students will engage with practical labs using simulators. - Emphasis on understanding hardware-software interaction, performance factors, and modern computer design trends. - The course is designed to prepare students for challenges in computer architecture and performance evaluation.